Digital Design Studio

Verilog & SystemVerilog RTL development.

Windows · Linux · Cloud

SystemVerilog source with module hierarchy and signal outline in Digital Design Studio

Digital Design Studio keeps RTL, ISA in Flow Navigator, ALcad and Agent in one application.

Develop Verilog and SystemVerilog, run supported RTL simulations, and use ISA, Evolve, Agent, ALcad and vFactory in Digital Design Studio. RTL and CAD keep dedicated interfaces for each kind of work.

Write

Verilog and SystemVerilog development.

Edit .sv, .svh, .v, and .vh sources with module hierarchy and signal outlines nearby. Move from an instance to its source while keeping the surrounding design in view.

Design hierarchy

Design hierarchy

Navigate module instances and their source locations without losing the project structure.

Signal outline

Signal outline

Review inputs, outputs, and internal signals alongside the active source file.

HintsBox in SystemC files

In SystemC files, HintsBox shows a local outline and declaration suggestions, including sc_module classes. It does not resolve C++ semantics.

RTL simulation

Run RTL simulation on your PC.

The simulation runs on your PC and does not start a Cloud job. Digital Design Studio does not bundle the simulators. Running the simulators requires sign-in.

Testbench reported a failure

A testbench that reports a failure in its output is shown as Testbench reported a failure, even when the simulator exits normally. Previously it was shown as passed.

Analyze

Turn results into the next step.

Analysis is the shared result-inspection area for RTL and ISA work. Open Analysis from the left rail, choose a saved run, and select an artifact. The run list groups results by module.

Analysis report
Analysis navigator

Analysis navigator

Move between saved runs and their waveforms, schematics, performance results, and reports.

Metrics in context

Metrics in context

Perf reads perf.json for the selected run and displays the saved observations as metrics and charts.

Performance analysis

Compute ceilings and memory bandwidth.

Compare compute throughput and memory bandwidth in the Roofline view.

Performance analysis
Compute and memory limits

Compute and memory limits

Locate measured kernels against compute ceilings and memory bandwidth.

Chart layers

Chart layers

Choose the limits, kernels and labels shown alongside the run summary.

Recorded results

Timing, PPA, and evidence share one Signoff view.

It presents available metrics, requirements, and missing sections. A UI verdict or estimate is a review aid, not independent timing closure, manufacturing approval, or formal signoff.

Recorded timing, PPA and evidence results of a saved analysis run
Recorded values

Recorded values

Compare WNS, TNS and failing paths on one scale for each recorded unit. Review saved timing, PPA and evidence values as recorded, without a calculated release verdict.

Ask

Work with Agent beside your design.

Agent answers in the AI panel and in its own window. When project reads are set to ask, it requests your approval before reading project files.

Agent in the AI panel beside a SystemVerilog source, with the weekly QUOTA
Ask Agent beside your design

Ask Agent beside your design

Search starts off for both Agent and Own API key. Agent does not grant an engine or permission that the selected host lacks.

ALcad

Move into CAD in the same application.

Choose ALcad workspaces from the workspace menu: Schematic, PCB Layout, 3D CAD, 3D Assembly and SI / PI Analysis. Wafer Process & Fab, which was under ALcad before, is now in vFactory. ALcad keeps its name and dedicated UI; available actions depend on the host and release, and the SI / PI workspace does not run a solver in this release.

Work on electronic circuits in the ALcad workspace inside Digital Design Studio.
Circuit workspace

Circuit workspace

Explore components and their connections on the schematic canvas.

Component properties

Component properties

Inspect the selected component and its circuit parameters.

vFactory is a new area next to DDS and ALcad for wafer processes and fabs. Explore vFactory

See how the work connects

From RTL source to circuits and analysis.

Saved result tabs

Saved result tabs that are too narrow for the whole run name keep a short part that tells them apart, such as …1 and …2, and the tooltip shows the full name. Saved results with the same title show which run they belong to, also in search.

Live Run

Live Run

Select Live Run in the project navigation to inspect the run surface the selected host offers. Use Search windows to filter the project window list.

Weekly QUOTA

Weekly QUOTA

Usage shows the active allowance, remaining amount and reset for the selected organization. Weekly QUOTA uses seven-day cycles.

Split Editor Right

When the tab menu offers Split Editor Right, use it to place the source and its schematic or report side by side. Reports preserve the run context and expose artifact content.

Flow Navigator

Flow Navigator

In DDS, open Flow Navigator and choose the required function. Bring RTL/SystemVerilog development and ISA design into one workspace; ISA Design flows open from the Flow Navigator. ISA uses the Digital Design Studio shell, settings, tabs, and bottom panel.

Follow every connection.

Trace modules, ports, and nets through the schematic. Switch to the 3D hierarchy to see how the pieces of a larger design fit together.

Where features run

Each host offers what it supports.

Some features run only on specific hosts. Where a host lacks one, Digital Design Studio says so instead of starting a run.

  • ISA Design in the Flow Navigator: RISC-V import with RV64, IM and A profiles.
  • QEDA (research models for superconducting transmons and CPW): OpenQASM circuit import on the Windows and Linux desktop; parametric layout and electromagnetic analysis on the Linux desktop only. Not available on Cloud.
  • Built-in HLS (an integer C subset to RTL): Linux desktop only. Synthesizing or simulating the generated RTL is not connected yet.
  • Evolve virtual FPGA candidate search: Linux desktop only.
  • UVM runs are not available on Cloud, and RTL-to-GDS physical runs are not available in this release.
  • Project link sharing (Cloud, personal projects): sign-in required, read access by default, links expire after 24 hours. Participants cannot run jobs, it is not real-time co-editing, and NDA-protected projects cannot be shared.
  • Private error reports: offered only after a serious crash or a failed save. Nothing is sent until you review the report and choose Send; sent reports are deleted after 30 days.
  • Display languages: the app offers the same 14 languages as this site. In the nine newer ones (Spanish, Simplified Chinese, German, Portuguese (Brazil), Hindi, Vietnamese, French, Indonesian and Italian), screens that are not translated yet show English.

Choose where you work

Choose your workspace.

Use the desktop app, open a Cloud workspace, or bring the CLI into your automation.

Desktop

Work with local files in Digital Design Studio on Windows or Linux. On Windows, updates from 2.1.2 to later versions no longer ask you to restart Windows. Before the install starts, open files keep a recovery copy of unsaved changes. Work that cannot be kept, such as unsaved vFactory or ALcad work, is listed first, and the update continues only if you choose Update anyway.

Choose your download

Cloud

Sign in to Altifigence and open your workspace from the browser. When you return to a Cloud window, its editors and an RTL schematic that is being prepared stay as they were instead of loading again. In production builds, the code downloaded for the Cloud start page before you sign in dropped from 1.18 MB to 0.72 MB (gzip), and for the project list from 1.25 MB to 0.79 MB.

Open Cloud

Start with your next design

Bring your project into view.