RTL to vFactoryPlatform EDA, CAD, dan simulasi generasi berikutnya

Dari desain RTL ke sirkuit, PCB, 3D (ALcad), hingga simulasi proses dan pabrik (pabrik virtual), semuanya terhubung dalam satu aplikasi Digital Design Studio.

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rtl altifigence-v002 LLM rtl core cvo CVO_top.sv
41module CVO_top (
// The sub_emax bf16_add (align + 25-bit add + normalize) is the integrated worst
// path; even after the 1a/1b split the align+add together were too long, so the
// barrel-shift align and the 25-bit add are now separated by their own register
// (sa0 holds the sign-extended aligned operands). Latency +1, bit-identical.
bf16_t sa_av_wire, sa_bv_wire;
logic [ 7:0] sa_emax_wire;
logic [23:0] sa_aa_wire, sa_ba_wire;
always_comb begin : comb_sub_emax_align
sa_av_wire = to_bf16(in_data_s0);
sa_bv_wire = to_bf16({~in_emax_s0[15], in_emax_s0[14:0]}); // -e_max
sa_emax_wire = (sa_av_wire.exp > sa_bv_wire.exp) ? sa_av_wire.exp : sa_bv_wire.exp;
sa_aa_wire = align_to_emax(sa_av_wire, sa_emax_wire);
sa_ba_wire = align_to_emax(sa_bv_wire, sa_emax_wire);
end
// Stage sa0 — register the sign-extended aligned operands (align off the adder).
logic signed [24:0] sa0_aa, sa0_ba;
logic [ 7:0] sa0_emax;
logic [15:0] sa0_pass;
logic sa0_subemax;
logic sa0_valid;
always_ff @(posedge clk) begin
if (!rst_n || i_clear) begin
sa0_valid <= 1'b0;
end else begin
sa0_aa <= $signed({sa_aa_wire[23], sa_aa_wire});
sa0_ba <= $signed({sa_ba_wire[23], sa_ba_wire});
sa0_emax <= sa_emax_wire;
sa0_pass <= in_data_s0;
sa0_subemax <= uop_flags.sub_emax;
sa0_valid <= in_valid_s0;
end
end
// Stage 1a-back — the 25-bit signed add, now isolated on its own register stage.
logic signed [24:0] sa_sum;
logic [ 7:0] sa_emax;
logic [15:0] sa_pass; // in_data_s0 carried for the non-sub_emax case
logic sa_subemax;
logic sa_valid;
always_ff @(posedge clk) begin
if (!rst_n || i_clear) begin
sa_valid <= 1'b0;
end else begin
sa_sum <= sa0_aa + sa0_ba;
sa_emax <= sa0_emax;
sa_pass <= sa0_pass;
sa_subemax <= sa0_subemax;
sa_valid <= sa0_valid;
end
end
altifigence_npu_top · 3f9c2a1eShow90%
clk_corerst_n_core6460256256256m_axisu_npu_frontendctrl_npu_frontendclkrst_ninst_data[63:0]instruction[63:0]kicku_decoderctrl_npu_decoderinstruction[63:0]kickgemm_validgemv_validcvo_validop_x64[59:0]u_Global_SchedulerGlobal_Schedulerclkrst_nissue_validgemm_readygemv_readycvo_readyu_systolic_engineGEMM_systolic_topvalidop[59:0]weight[255:0]data[255:0]result[255:0]doneu_GEMV_topGEMV_topvalidop[59:0]data[255:0]result[255:0]doneu_CVO_topCVO_topvalidop[59:0]data[255:0]result[255:0]doneu_mem_dispatchermem_dispatcherclkrst_ns_axi[511:0]weight[255:0]data[255:0]read_validwrite_readyu_norm_lowergemm_result_normalizerdata[255:0]validout[255:0]readyu_packerFROM_gemm_result_packergemm[255:0]gemv[255:0]cvo[255:0]m_axis[255:0]m_valid
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Sample workspaceCVO_top.sv · Ln 123, Col 1 · SplitSystemVerilog
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