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DESIGN MODULES

temp_code_space

altifigence_npu_top:41

u_npu_controller_topnpu_controller_top:89

u_Global_SchedulerGlobal_Scheduler:122

u_mem_dispatchermem_dispatcher:206

u_HP_buffermem_HP_buffer:247

u_fmap_prepreprocess_fmap:269

u_systolic_engineGEMM_systolic_top:305

u_sign_recGEMM_sign_recovery:350

u_norm_lowergemm_result_normalizer:356

u_norm_uppergemm_result_normalizer:366

u_CVO_topCVO_top:506

CVO_top:41

Constants / headers0

SUBMODULES38

AXIL_CMD_IN:31

AXIL_STAT_OUT:29

barrel_shifter_BF16:20

ctrl_npu_decoder:27

ctrl_npu_frontend:24

CVO_cordic_unit:26

CVO_sfu_unit:31

CVO_top:41

fmap_cache:30

FROM_gemm_result_packer:28

SOURCE FILES85

SVAlgorithms.sv

SValtifigence_npu_top.sv

SVAXIL_CMD_IN.sv

SVAXIL_STAT_OUT.sv

SVbarrel_shifter_BF16.sv

SVBF16_math.sv

CONSTRAINTS0

PROJECT CONFIGURATION1

DOCUMENTS0

PHYSICAL DESIGN1

TESTBENCHES

Select a design module, then Ctrl+click testbenches to link them.

tb_CVO_top_golden:26

tb_barrel_shifter_BF16:21

tb_ctrl_npu_decoder:19

tb_v002_runtime_smoke_program:17

41module CVO_top (

// The sub_emax bf16_add (align + 25-bit add + normalize) is the integrated worst

// path; even after the 1a/1b split the align+add together were too long, so the

// barrel-shift align and the 25-bit add are now separated by their own register

// (sa0 holds the sign-extended aligned operands). Latency +1, bit-identical.

bf16_t sa_av_wire, sa_bv_wire;

logic [ 7:0] sa_emax_wire;

logic [23:0] sa_aa_wire, sa_ba_wire;

always_comb begin : comb_sub_emax_align

sa_av_wire = to_bf16(in_data_s0);

sa_bv_wire = to_bf16({~in_emax_s0[15], in_emax_s0[14:0]}); // -e_max

sa_emax_wire = (sa_av_wire.exp > sa_bv_wire.exp) ? sa_av_wire.exp : sa_bv_wire.exp;

sa_aa_wire = align_to_emax(sa_av_wire, sa_emax_wire);

sa_ba_wire = align_to_emax(sa_bv_wire, sa_emax_wire);

end

// Stage sa0 — register the sign-extended aligned operands (align off the adder).

logic signed [24:0] sa0_aa, sa0_ba;

logic [ 7:0] sa0_emax;

logic [15:0] sa0_pass;

logic sa0_subemax;

logic sa0_valid;

always_ff @(posedge clk) begin

if (!rst_n || i_clear) begin

sa0_valid <= 1'b0;

end else begin

sa0_aa <= $signed({sa_aa_wire[23], sa_aa_wire});

sa0_ba <= $signed({sa_ba_wire[23], sa_ba_wire});

sa0_emax <= sa_emax_wire;

sa0_pass <= in_data_s0;

sa0_subemax <= uop_flags.sub_emax;

sa0_valid <= in_valid_s0;

end

// Stage 1a-back — the 25-bit signed add, now isolated on its own register stage.

logic signed [24:0] sa_sum;

logic [ 7:0] sa_emax;

logic [15:0] sa_pass; // in_data_s0 carried for the non-sub_emax case

logic sa_subemax;

logic sa_valid;

always_ff @(posedge clk) begin

if (!rst_n || i_clear) begin

sa_valid <= 1'b0;

end else begin

sa_sum <= sa0_aa + sa0_ba;

sa_emax <= sa0_emax;

sa_pass <= sa0_pass;

sa_subemax <= sa0_subemax;

sa_valid <= sa0_valid;

end

Executive summary

altifigence_npu_top · Full bundle B

This stored analysis run brings together 12 artifacts. The report links each observation to the source artifact.

Waveform capture B	Signals 148
Schematic snapshot B	Instances 42
seed-full-analysis-run	Kernels 6
Path analyzer B	Paths 31
Memory dump B	Regions 6
Event timeline B	Events 11.1k
Perf chart B	MAC avg 44.2%
Timing report B	WNS -0.07 ns
PPA snapshot B	Power 21.3 W
Evidence bundle B	Claims 14
Data flow B	Nodes 36
3D canvas B	Grid 32 × 32

Module	altifigence_npu_top
Source	rtl/altifigence-v002/LLM/rtl/top/altifigence_npu_top.sv
Run	altifigence-npu-full-v003
Named view	Full bundle B
Artifacts	12

Methodology

The report reads the saved analysis bundle and reorganizes its metrics, detail rows, and notes into document sections.

Each artifact retains its own units and status. Compare neighboring metrics within the same artifact, then follow its source path to the stored evidence.

Waveform	signal transitions and capture timing
Schematic	module connections and structural evidence
Roofline	compute throughput and arithmetic intensity
Path	critical paths and timing evidence
Memory	memory traffic and bandwidth
Events	recorded event activity
Perf	performance samples and utilization trends
Timing	timing margins
PPA	power, performance, and area estimates
Signoff	stored validation evidence
Data Flow	data movement between compute stages
3D Canvas	stored spatial and placement evidence

Findings register

Flagged metrics from the stored artifacts.

Waveform · MAC util	47.5%
Waveform · Stalls	518
Schematic · Inline	1
Schematic · Diagnostics	2
Path · Worst slack	-0.07 ns
Path · Logic levels	14
Path · Fanout	26
Memory · Reads	1.4 GB/s
Memory · Writes	1.6 GB/s
Events · MAC	36%
Events · Stalls	18%
Perf · MAC avg	44.2%
Perf · L2 write	39.6%
Timing · WNS	-0.07 ns
Timing · TNS	-0.41 ns
Timing · Failing	3
PPA · Power	21.3 W
PPA · LUT util	67%
PPA · DSP util	79%
PPA · Freq	950 MHz
Signoff · Passed	10
Signoff · Open	4
Signoff · Coverage	78%
Data Flow · Edges	63
Data Flow · Max depth	11
Data Flow · Hot path	HP→DISP→MAC
3D Canvas · Avg util	41.7%
3D Canvas · Peak PE	99%
3D Canvas · Idle PEs	173

Report summary

Waveform capture B	Signals 148
Schematic snapshot B	Instances 42
seed-full-analysis-run	Kernels 6
Path analyzer B	Paths 31
Memory dump B	Regions 6
Event timeline B	Events 11.1k
Perf chart B	MAC avg 44.2%
Timing report B	WNS -0.07 ns
PPA snapshot B	Power 21.3 W
Evidence bundle B	Claims 14
Data flow B	Nodes 36
3D canvas B	Grid 32 × 32

01Waveform

Waveform capture B

4 metrics · 2 rows · 0 notes

4981200 cycles · 32 cores · higher stall density

Interpretation

The Waveform section reviews signal transitions and capture timing. It reorganizes 4 metric(s), 2 detail row(s), and 0 note(s) from the “Waveform capture B” artifact into report form.

The first observation is MAC util = 47.5%. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Waveform section contains critical-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is MAC util = 47.5%, and source path is analyze/altifigence-npu-full-v003/waveform.json. The interpretation is linked to stored analysis output.

The “Waveform capture B” result in Waveform requires additional review. Compare MAC util = 47.5% against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Waveform requires careful interpretation. MAC util = 47.5% and 2 flagged metric(s) remain the main review points.

Metrics

Signals	148
Ticks	4.98M
MAC util	47.5%
Stalls	518

Details

Top scope	u_gemm_systolic_top
Playhead	cycle 90210

analyze/altifigence-npu-full-v003/waveform.json

02Schematic

Schematic snapshot B

4 metrics · 0 rows · 0 notes

Same hierarchy with fewer expanded inline blocks

Interpretation

The Schematic section reviews module connections and structural evidence. It reorganizes 4 metric(s), 0 detail row(s), and 0 note(s) from the “Schematic snapshot B” artifact into report form.

The first observation is Inline = 1. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Schematic section contains warning-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Inline = 1, and source path is analyze/altifigence-npu-full-v003/schematic.json. The interpretation is linked to stored analysis output.

The “Schematic snapshot B” result in Schematic requires additional review. Compare Inline = 1 against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Schematic requires careful interpretation. Inline = 1 and 2 flagged metric(s) remain the main review points.

Metrics

Instances	42
Nets	186
Inline	1
Diagnostics	2

analyze/altifigence-npu-full-v003/schematic.json

03Roofline

seed-full-analysis-run

4 metrics · 0 rows · 0 notes

Full bundle B · altifigence_npu_top

Interpretation

The Roofline section reviews compute throughput and arithmetic intensity. It reorganizes 4 metric(s), 0 detail row(s), and 0 note(s) from the “seed-full-analysis-run” artifact into report form.

The first observation is Kernels = 6. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 0.

Read the Roofline metrics alongside the stored evidence and neighboring artifacts.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Kernels = 6, and source path is analyze/altifigence-npu-full-v003/roofline.json. The interpretation is linked to stored analysis output.

The source artifact preserves the values shown in this report.

AI opinion

AI opinion: compare Kernels = 6 with neighboring artifacts before drawing a conclusion.

Metrics

Kernels	6
Intensity	11.8
Achieved	15.1 GOPS
Avg util	41.7%

analyze/altifigence-npu-full-v003/roofline.json

04Path

Path analyzer B

4 metrics · 2 rows · 0 notes

Weight dispatcher queue path is tighter

Interpretation

The Path section reviews critical paths and timing evidence. It reorganizes 4 metric(s), 2 detail row(s), and 0 note(s) from the “Path analyzer B” artifact into report form.

The first observation is Worst slack = -0.07 ns. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 3.

The Path section contains critical-level signals. Use the 3 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Worst slack = -0.07 ns, and source path is analyze/altifigence-npu-full-v003/path-analyzer.json. The interpretation is linked to stored analysis output.

The “Path analyzer B” result in Path requires additional review. Compare Worst slack = -0.07 ns against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Path requires careful interpretation. Worst slack = -0.07 ns and 3 flagged metric(s) remain the main review points.

Metrics

Paths	31
Worst slack	-0.07 ns
Logic levels	14
Fanout	26

Details

Start	GEMM_weight_dispatcher/clk
End	mem_u_operation_queue/push

analyze/altifigence-npu-full-v003/path-analyzer.json

05Memory

Memory dump B

4 metrics · 2 rows · 0 notes

HP buffer pressure elevated

Interpretation

The Memory section reviews memory traffic and bandwidth. It reorganizes 4 metric(s), 2 detail row(s), and 0 note(s) from the “Memory dump B” artifact into report form.

The first observation is Reads = 1.4 GB/s. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Memory section contains warning-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Reads = 1.4 GB/s, and source path is analyze/altifigence-npu-full-v003/memory.json. The interpretation is linked to stored analysis output.

The “Memory dump B” result in Memory requires additional review. Compare Reads = 1.4 GB/s against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Memory requires careful interpretation. Reads = 1.4 GB/s and 2 flagged metric(s) remain the main review points.

Metrics

Regions	6
Reads	1.4 GB/s
Writes	1.6 GB/s
Watches	3

Details

Hot region	HP Buffer FIFO
Cursor	0x1000_0140

analyze/altifigence-npu-full-v003/memory.json

06Events

Event timeline B

4 metrics · 2 rows · 0 notes

More systolic stalls in mid window

Interpretation

The Events section reviews recorded event activity. It reorganizes 4 metric(s), 2 detail row(s), and 0 note(s) from the “Event timeline B” artifact into report form.

The first observation is MAC = 36%. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Events section contains critical-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is MAC = 36%, and source path is analyze/altifigence-npu-full-v003/events.json. The interpretation is linked to stored analysis output.

The “Event timeline B” result in Events requires additional review. Compare MAC = 36% against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Events requires careful interpretation. MAC = 36% and 2 flagged metric(s) remain the main review points.

Metrics

Events	11.1k
Cycles	220
MAC	36%
Stalls	18%

Details

Peak lane	SYSTOLIC_STALL
Marker	cycle 142

analyze/altifigence-npu-full-v003/events.json

07Perf

Perf chart B

4 metrics · 0 rows · 0 notes

Lower MAC util with heavier DMA write share

Interpretation

The Perf section reviews performance samples and utilization trends. It reorganizes 4 metric(s), 0 detail row(s), and 0 note(s) from the “Perf chart B” artifact into report form.

The first observation is MAC avg = 44.2%. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Perf section contains warning-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is MAC avg = 44.2%, and source path is analyze/altifigence-npu-full-v003/perf.json. The interpretation is linked to stored analysis output.

The “Perf chart B” result in Perf requires additional review. Compare MAC avg = 44.2% against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Perf requires careful interpretation. MAC avg = 44.2% and 2 flagged metric(s) remain the main review points.

Graph

Metrics

MAC avg	44.2%
L2 read	35.8%
L2 write	39.6%
Samples	256

analyze/altifigence-npu-full-v003/perf.json

08Timing

Timing report B

4 metrics · 2 rows · 0 notes

Post-impl summary — one failing path cluster

Interpretation

The Timing section reviews timing margins. It reorganizes 4 metric(s), 2 detail row(s), and 0 note(s) from the “Timing report B” artifact into report form.

The first observation is WNS = -0.07 ns. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 3.

The Timing section contains critical-level signals. Use the 3 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is WNS = -0.07 ns, and source path is analyze/altifigence-npu-full-v003/timing.json. The interpretation is linked to stored analysis output.

The “Timing report B” result in Timing requires additional review. Compare WNS = -0.07 ns against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Timing requires careful interpretation. WNS = -0.07 ns and 3 flagged metric(s) remain the main review points.

Metrics

WNS	-0.07 ns
TNS	-0.41 ns
Failing	3
Endpoints	18.2k

Details

LUT	43,910
DSP	528

analyze/altifigence-npu-full-v003/timing.json

09PPA

PPA snapshot B

4 metrics · 0 rows · 0 notes

Higher power for lower achieved throughput

Interpretation

The PPA section reviews power, performance, and area estimates. It reorganizes 4 metric(s), 0 detail row(s), and 0 note(s) from the “PPA snapshot B” artifact into report form.

The first observation is Power = 21.3 W. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 4.

The PPA section contains critical-level signals. Use the 4 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Power = 21.3 W, and source path is analyze/altifigence-npu-full-v003/ppa.json. The interpretation is linked to stored analysis output.

The “PPA snapshot B” result in PPA requires additional review. Compare Power = 21.3 W against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: PPA requires careful interpretation. Power = 21.3 W and 4 flagged metric(s) remain the main review points.

Metrics

Power	21.3 W
LUT util	67%
DSP util	79%
Freq	950 MHz

analyze/altifigence-npu-full-v003/ppa.json

10Signoff

Evidence bundle B

4 metrics · 0 rows · 1 notes

Regression vs bundle A on stall and timing claims

Interpretation

The Signoff section reviews stored validation evidence. It reorganizes 4 metric(s), 0 detail row(s), and 1 note(s) from the “Evidence bundle B” artifact into report form.

The first observation is Passed = 10. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 3.

The Signoff section contains critical-level signals. Use the 3 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Passed = 10, and source path is analyze/altifigence-npu-full-v003/evidence.json. The interpretation is linked to stored analysis output.

The “Evidence bundle B” result in Signoff requires additional review. Compare Passed = 10 against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Signoff requires careful interpretation. Passed = 10 and 3 flagged metric(s) remain the main review points.

Metrics

Claims	14
Passed	10
Open	4
Coverage	78%

Notes

Regression: timing closure and stall-rate claims diverged from bundle A.

analyze/altifigence-npu-full-v003/evidence.json

11Data Flow

Data flow B

4 metrics · 3 rows · 1 notes

HP buffer back-pressure adds a feedback edge into the dispatcher

Interpretation

The Data Flow section reviews data movement between compute stages. It reorganizes 4 metric(s), 3 detail row(s), and 1 note(s) from the “Data flow B” artifact into report form.

The first observation is Edges = 63. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 3.

The Data Flow section contains critical-level signals. Use the 3 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Edges = 63, and source path is analyze/altifigence-npu-full-v003/dataFlow.json. The interpretation is linked to stored analysis output.

The “Data flow B” result in Data Flow requires additional review. Compare Edges = 63 against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: Data Flow requires careful interpretation. Edges = 63 and 3 flagged metric(s) remain the main review points.

Metrics

Nodes	36
Edges	63
Max depth	11
Hot path	HP→DISP→MAC

Details

Source node	axi_hp_weight_dma
Sink node	result_packer
Feedback	hp_buffer_full → dispatcher

Notes

Back-pressure feedback edge present in this run; raises the longest dependency chain to 11.

analyze/altifigence-npu-full-v003/dataFlow.json

123D Canvas

3D canvas B

4 metrics · 2 rows · 1 notes

Hot cluster in the south-east quadrant from DMA write stalls

Interpretation

The 3D Canvas section reviews stored spatial and placement evidence. It reorganizes 4 metric(s), 2 detail row(s), and 1 note(s) from the “3D canvas B” artifact into report form.

The first observation is Avg util = 41.7%. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 3.

The 3D Canvas section contains critical-level signals. Use the 3 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 metric evidence item(s). The representative metric is Avg util = 41.7%, and source path is analyze/altifigence-npu-full-v003/canvas3d.json. The interpretation is linked to stored analysis output.

The “3D canvas B” result in 3D Canvas requires additional review. Compare Avg util = 41.7% against neighboring artifacts and inspect the detailed path in the full viewer.

AI opinion

AI opinion: 3D Canvas requires careful interpretation. Avg util = 41.7% and 3 flagged metric(s) remain the main review points.

Metrics

Grid	32 × 32
Avg util	41.7%
Peak PE	99%
Idle PEs	173

Details

Hottest tile	row 27 · col 29
Cold band	cols 0–6 starved

Notes

Utilisation skewed: a hot SE cluster coexists with a starved west band under heavier DMA writes.

analyze/altifigence-npu-full-v003/canvas3d.json

Traceability matrix

Waveform capture B	analyze/altifigence-npu-full-v003/waveform.json
Schematic snapshot B	analyze/altifigence-npu-full-v003/schematic.json
seed-full-analysis-run	analyze/altifigence-npu-full-v003/roofline.json
Path analyzer B	analyze/altifigence-npu-full-v003/path-analyzer.json
Memory dump B	analyze/altifigence-npu-full-v003/memory.json
Event timeline B	analyze/altifigence-npu-full-v003/events.json
Perf chart B	analyze/altifigence-npu-full-v003/perf.json
Timing report B	analyze/altifigence-npu-full-v003/timing.json
PPA snapshot B	analyze/altifigence-npu-full-v003/ppa.json
Evidence bundle B	analyze/altifigence-npu-full-v003/evidence.json
Data flow B	analyze/altifigence-npu-full-v003/dataFlow.json
3D canvas B	analyze/altifigence-npu-full-v003/canvas3d.json

Technical conclusion

The Perf artifact reports MAC avg = 44.2%, with two metrics flagged for review. Compare the heavier DMA write share against the Memory and Waveform artifacts.

Waveform · MAC util	47.5%
Waveform · Stalls	518
Schematic · Inline	1
Schematic · Diagnostics	2
Path · Worst slack	-0.07 ns
Path · Logic levels	14
Path · Fanout	26
Memory · Reads	1.4 GB/s
Memory · Writes	1.6 GB/s
Events · MAC	36%
Events · Stalls	18%
Perf · MAC avg	44.2%
Perf · L2 write	39.6%
Timing · WNS	-0.07 ns
Timing · TNS	-0.41 ns
Timing · Failing	3
PPA · Power	21.3 W
PPA · LUT util	67%
PPA · DSP util	79%
PPA · Freq	950 MHz
Signoff · Passed	10
Signoff · Open	4
Signoff · Coverage	78%
Data Flow · Edges	63
Data Flow · Max depth	11
Data Flow · Hot path	HP→DISP→MAC
3D Canvas · Avg util	41.7%
3D Canvas · Peak PE	99%
3D Canvas · Idle PEs	173

07 Perf chart B

The representative metric for 07 Perf chart B is MAC avg = 44.2%. This category expands into lower artifact nodes in document form.

Reading focus

TOP

You are at the top of 07 Perf chart B. Confirm what artifact or report stage this category represents before reading details.

Current artifact

Artifact	Perf
Metric	MAC avg 44.2%
Status	WARN

9 Cells20/20 NetsrtlRoutes: ✓

altifigence_npu_top

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<40s

तेज़ AST इंडेक्सिंग¹

लाखों लाइनों वाले बड़े RTL कोडबेस और मॉड्यूल की 40 सेकंड से कम में इन्क्रिमेंटल पार्सिंग

100%

सिंटैक्स अनुरूपता²

निर्धारित IEEE 1800-2017 SystemVerilog सिंटैक्स रिग्रेशन सूट के सभी केस पास

10x

कम समय वाले सत्यापन चक्र³

सिंथेसिस से पहले स्वचालित DRC और CDC विश्लेषण से डिबगिंग चक्र घटाएँ

Zero

विक्रेता पर निर्भरता के बिना खुले इंटरफ़ेस⁴

मौजूदा पाइपलाइन को MCP और CLI से जोड़ें

आपकी पसंद का AI। आपके परिचित डिज़ाइन टूल।

AI मॉडल एकीकरण⁵

समर्थित तकनीकें और टूल⁵

Altifigence से डिज़ाइन किया गया ओपन-सोर्स हार्डवेयर⁶

Altifigence टूलचेन से सिंथेसाइज़ और सत्यापित किया गया ओपन-सोर्स हार्डवेयर संदर्भ प्रोजेक्ट।

PCCX.ai प्रोजेक्ट दस्तावेज़ GitHub

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रिलीज़ नोट्स

Altifigence Docs

Digital Design Studio

स्थानीय काम को प्राथमिकता देने वाला SystemVerilog और Verilog IDE
RTL सिमुलेशन, ट्रेस और VCD वेवफ़ॉर्म जाँच
Flow Navigator में ISA डिज़ाइन और Evolve
प्रोजेक्ट पढ़ने से पहले मंज़ूरी लेने वाला Agent

ALcad

एक CAD कार्यस्थान में स्कीमैटिक और PCB लेआउट
3D CAD और 3D असेंबली कार्यस्थान
सर्किट सिमुलेशन और निर्माता SPICE मॉडल इंपोर्ट
Gerber X2 और Excellon ड्रिल फ़ाइल आउटपुट

Altifigence Cloud

ब्राउज़र में प्रोजेक्ट कार्यस्थान
CLI और MCP एकीकरण
Cloud रन और Agent के लिए साझा साप्ताहिक QUOTA
डिफ़ॉल्ट रूप से पढ़ने की अनुमति वाला प्रोजेक्ट लिंक साझाकरण

डेवलपर प्लेटफ़ॉर्म

Altifigence के साथ बनाएँ

अपने चिप विकास के लिए Evolve सहित Digital Design Studio, ALcad, Cloud, API, CLI और MCP देखें।

दस्तावेज़

डेवलपर दस्तावेज़

AST विश्लेषण और सिंथेसिस की तकनीकी गाइड, उत्पाद संदर्भ, API और CLI विनिर्देश तथा MCP एकीकरण।

निवेश और साझेदार

निवेश और साझेदारी संबंधी पूछताछ

निवेशकों, वैश्विक साझेदारों और इकोसिस्टम सहयोग के लिए कंपनी जानकारी और आधिकारिक संपर्क माध्यम।

01 / डिजिटल डिज़ाइननिःशुल्क · परिचयात्मक

डिजिटल लॉजिक परिपथ

डिजिटल संकेत और AND, OR, XOR जैसे गेटों से शुरू करके संयोजन परिपथ, लैच, फ्लिप-फ्लॉप, काउंटर और अवस्था मशीन बनाएँ। सत्य सारणी, सूत्र, परिपथ और तरंगरूप को सीधे जोड़ें तथा RTL अभ्यास से जाँचें। वैकल्पिक उन्नत पाठ डेटा-पथ और इंटरफ़ेस तक विस्तार करते हैं।

संयोजन और अनुक्रमिक लॉजिकSystemVerilog

पाठ्यक्रम देखें

02 / डिजिटल डिज़ाइननिःशुल्क · बुनियादी

RTL डिज़ाइन की बुनियाद

डिजिटल परिपथों को SystemVerilog में लिखें। प्रकार, बिट चौड़ाई, चिह्न, संयोजन और अनुक्रमिक तर्क, मॉड्यूल, पैरामीटर तथा generate सीखें। स्वतंत्र टेस्टबेंच से सीमा और त्रुटियाँ जाँचें, फिर आवर्ती पल्स को संचायक से जोड़कर दोहराए जा सकने वाले परिणाम सुरक्षित करें।

SystemVerilogमॉड्यूल डिज़ाइन

पाठ्यक्रम देखें

03 / डिजिटल डिज़ाइनIn preparation

RTL Design: Datapaths & Pipelines

Build a small computing system by connecting arithmetic and control, then explore pipelined execution.

DatapathsPipelines

पाठ्यक्रम देखें

¹AST प्रदर्शन मापने का परिवेश और दायरा
“40 सेकंड से कम” वह इन्क्रिमेंटल AST अपडेट समय है जब Digital Design Studio, 8 वर्चुअल CPU, 32 GiB मेमोरी और Ubuntu 24.04 LTS वाले क्लाउड में PCCX v002 की पूर्वनिर्धारित RTL बदलाव को प्रोसेस करता है। यह शुरुआती विश्लेषण और 3 वार्म-अप रन के बाद समान शुरुआती स्थिति और बदलाव की शर्तों पर 30 मापों का माध्यिका मान है। शुरुआती पूर्ण विश्लेषण, प्रोजेक्ट अपलोड और नेटवर्क ट्रांसफ़र समय शामिल नहीं हैं। वास्तविक समय प्रोजेक्ट संरचना, बदलाव के दायरे, कैश और सर्वर संसाधनों से बदल सकता है।
²परीक्षण सफलता दर और भाषा समर्थन का दायरा
“100%” मापे गए Digital Design Studio बिल्ड में PCCX v002 आधारित पूर्वनिर्धारित SystemVerilog सिंटैक्स रिग्रेशन परीक्षण के सभी निर्धारित मामलों में अपेक्षित परिणाम पाने वाले मामलों का अनुपात है। विफल या छोड़े गए मामले सफल नहीं गिने जाते। यह केवल निर्धारित परीक्षण दायरे पर लागू है; पूरे SystemVerilog मानक का अनुपालन, सिमुलेशन या सिंथेसिस की शुद्धता या तृतीय-पक्ष टूल से पूर्ण संगतता नहीं दर्शाता। Sail समर्थन और सत्यापन इसमें शामिल नहीं हैं।
³तुलना का आधार और प्रदर्शन मापन विधि
“10× तक” समान क्लाउड और Digital Design Studio बिल्ड में PCCX v002 के पूर्वनिर्धारित बदलावों के लिए पूर्ण पुनर्विश्लेषण और इन्क्रिमेंटल विश्लेषण के सत्यापन फ़ीडबैक समय की तुलना है। दोनों में समान DRC/CDC जाँच दायरा और मानदंड हैं। हर विधि के लिए 3 वार्म-अप के बाद 30 मापों का माध्यिका समय लिया जाता है। अनुपात पूर्ण पुनर्विश्लेषण की माध्यिका को इन्क्रिमेंटल माध्यिका से भाग देकर मिलता है; प्रकाशित मान पूर्वनिर्धारित परिदृश्यों में सबसे अधिक है। इसका अर्थ पूरे डिज़ाइन और सत्यापन चक्र में उतनी ही कमी नहीं है। परिणाम डिज़ाइन और रन परिवेश के अनुसार बदल सकते हैं।
⁴इंटरफ़ेस एकीकरण का दायरा
“खुलापन” का अर्थ है कि Digital Design Studio अपने MCP इंटरफ़ेस और CLI कमांड से बाहरी टूल और ऑटोमेशन पाइपलाइन जोड़ सकता है। उपलब्ध सुविधाएँ और दायरा उत्पाद संस्करण, लक्ष्य कॉन्फ़िगरेशन, अनुमतियों और लाइसेंस शर्तों के अनुसार बदल सकते हैं। इसका अर्थ पूरा उत्पाद ओपन सोर्स होना या हर बाहरी टूल से संगत होना नहीं है।
⁵ट्रेडमार्क और लाइसेंस सूचना
दिखाए गए तृतीय-पक्ष नाम और लोगो के अधिकार उनके धारकों के पास हैं। इन्हें समर्थित तकनीक और एकीकरण पहचानने के लिए दिखाया गया है। स्पष्ट उल्लेख के बिना ये उन संस्थाओं और Altifigence के बीच साझेदारी, प्रायोजन, प्रमाणन या गारंटी नहीं दर्शाते। हर तकनीक और टूल पर उसके अधिकार धारक की लाइसेंस और उपयोग शर्तें लागू हैं।
⁶ओपन-सोर्स हार्डवेयर उपयोग की शर्तें
PCCX v002 से जुड़े सार्वजनिक सोर्स कोड पर संबंधित रिपॉज़िटरी के लाइसेंस और सूचनाएँ लागू हैं। लिंक किया गया KV260 एकीकरण प्रोजेक्ट Apache License 2.0 के अंतर्गत है; किसी फ़ाइल या बाहरी घटक का अलग लाइसेंस हो तो उसकी शर्तें लागू होंगी। दस्तावेज़ और चित्रों के लिए प्रत्येक सामग्री का लाइसेंस देखें। सार्वजनिक सोर्स के उपयोग की अनुमति नाम या लोगो जैसे ट्रेडमार्क के उपयोग की अनुमति नहीं देती।

RTL to vFactoryअगली पीढ़ी का EDA, CAD और सिमुलेशन

Executive summary

Input lineage

Methodology

Findings register

Report summary

Waveform capture B

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Schematic snapshot B

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seed-full-analysis-run

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Path analyzer B

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Memory dump B

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Event timeline B

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Perf chart B

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Timing report B

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PPA snapshot B

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Evidence bundle B

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Data flow B

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3D canvas B

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Traceability matrix

Technical conclusion

आपकी पसंद का AI। आपके परिचित डिज़ाइन टूल।

Altifigence से डिज़ाइन किया गया ओपन-सोर्स हार्डवेयर⁶