Digital Design Studio 2.1.2: vFactory, a virtual fab next to your design, and traceable models in ALcad

Digital Design Studio 2.1.2 adds vFactory, a virtual fab you can walk through and simulate, beside DDS and ALcad. ALcad keeps a record of where imported models and manufacturing rules come from, and the process design kit picker shows each kit's origin.

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Digital Design Studio 2.1.2.1 is the first public build of version 2.1.2. It opens a third area beside DDS and ALcad. vFactory is a virtual semiconductor fab inside the same app: walk through a reference fab, watch a production simulation move through it, look inside an EUV scanner and see how a layout from DDS could turn into wafers.

ALcad now imports manufacturer models with a record of their source and checks boards against a sourced set of manufacturing rules, and the process design kit picker shows where each kit comes from. Here is what is new.

vFactory, a virtual fab next to your design

Open vFactory from the product menu to switch to the fab, just as you move between DDS and ALcad. The first view opens our own reference logic fab: 300 tools, including four EUV scanners, laid out at true size across four building levels: the cleanroom, the fan deck, the subfab and the utility floor.

You can resize the example to anywhere between 200 and 400 tools, or import a complete fab model and let vFactory lay out its zones, tool rows and the overhead rail network with its stockers and load ports. The reference fab is an original, synthetic example. It does not copy any company's plant, and every number in it is a documented assumption, so you can learn how a fab works without mistaking the example for real plant data.

Tools in the reference fab, by process area

300 tools in the default layout

Tools in the reference fab, by process area. Values are listed in the data table below.Lithography44Etch56Thin film64Diffusion16Implant16CMP20Wet clean36Metrology48
Source / method: vFactory reference fab in Digital Design Studio 2.1.2. Tool counts are our assumptions for a synthetic example fab, not data from a real plant.

Minimum — Diffusion: 16 tools. Maximum — Thin film: 64 tools.

Tools in the reference fab, by process area · Data · Unit: tools · Source: vFactory reference fab in Digital Design Studio 2.1.2. Tool counts are our assumptions for a synthetic example fab, not data from a real plant. · Period: Default 300-tool layout
CategoryValue (tools)
Lithography44
Etch56
Thin film64
Diffusion16
Implant16
CMP20
Wet clean36
Metrology48
  1. Lithography

    4 EUV scanners, 16 DUV scanners and 24 coat/develop tracks.

  2. Etch

    Dielectric and conductor etch.

  3. Thin film

    CVD, PVD and ALD deposition.

  4. Diffusion

    Diffusion and anneal furnaces that run lots in batches.

  5. Implant

    Ion implantation.

  6. CMP

    Planarization between layers.

  7. Wet clean

    Batch and single-lot wet cleaning.

  8. Metrology

    CD-SEM, overlay and film metrology, and defect inspection.

Walk through the fab

Choose Walk to enter at the gowning room, at eye height. Move with W, A, S and D or the arrow keys, hold Shift to go faster and press E to open a nearby door. Walls, doors and equipment block your way as they would in a real building, so the route through the air shower to the process floor feels like a visit rather than a fly-through.

Other views help you keep your bearings. The dollhouse view pulls the four floors apart, the 2D map stays the editable floor plan, and the minimap lets you pick a point and walk there. Tags describe tools and process zones, Measure reports distances and height differences in millimetres, and the stairs or the elevator take you between levels.

A guided tour of the reference fab

Play tour walks the route for you and pauses at each stop so you can read about it.

  1. Gowning and air shower

    The tour starts where every visit to a cleanroom begins, before you step onto the process floor.

  2. Lithography

    The patterning area, where a pattern is printed onto each layer of the wafer.

  3. Etch and thin film

    Tools that remove material and deposit new films, layer after layer.

  4. Diffusion and implant

    Furnaces and ion implanters that set the electrical properties of the silicon.

  5. CMP and wet processing

    Polishing and cleaning that prepare each surface for the next layer.

  6. Metrology

    Measurement and inspection tools that check the wafers between steps.

  7. EUV

    The tour ends at the EUV scanners, which print the most critical patterns.

Watch a fab simulation play out

Behind the scene runs a discrete-event fab simulation. Release lots into the reference fab and the engine schedules every step, including dispatching, batching, setups, breakdowns and maintenance. Runs are seeded, so the same model and the same seed always give the same result.

When a run finishes, play it back in the 3D fab. Pause, speed it up from real time to 100,000 times faster, or jump to any moment. Tool states, batches and FOUP moves between tools follow the engine's recorded events exactly, and the tool and lot inspectors show the values at the selected time next to the final results.

Selecting an etch tool or an inspection tool opens a small model built from public measured data, the BOSCH plasma etch and SECOM data sets. Each panel names its source, shows its inputs and test metrics, and is labelled as an educational demonstration.

Inside the EUV scanner

Each EUV scanner in the fab can be opened. The inside view shows the path of the light from the source to the wafer, lets you switch between NXE, High-NA and Hyper-NA, and takes the timing of the scan motion from the same budget engine that drives the calculations.

The EUV calculation panel follows the light budget: how much of the source's energy reaches the intermediate focus, how much survives the Mo/Si multilayer mirrors and how much reaches the wafer. Start from an editable example and see every assumption labelled as one.

From your layout to a virtual wafer

In Cloud, choose Send to vFactory in the DDS GDS viewer to see what a layout could mean on a 300 mm wafer. vFactory opens Design to wafer, computes the die map from the size of your layout, releases lots into the reference fab and reports yield with the Poisson, Murphy and clustered models, each with its defect-density assumption shown. Cycle times come from the fab simulation, and you can save the result with the project.

From layout to wafers

One path from a design in DDS to a yield estimate in vFactory.

01GDS layoutGDS layout02Wafer mapWafer map03Lots in the fabLots in the fab04Yield and delive…Yield and delivery01GDS layoutGDS layout02Wafer mapWafer map03Lots in the fabLots in the fab04Yield and delive…Yield and delivery
  1. GDS layout

    Choose a layout in DDS. Its size sets the die dimensions.

  2. Wafer map

    vFactory places the dies on a 300 mm wafer, scribe lines included.

  3. Lots in the fab

    Lots are released into the reference fab and scheduled step by step.

  4. Yield and delivery

    Poisson, Murphy and clustered yield, with cycle times from the simulation.

Traceable models and rules in ALcad

Manufacturer SPICE models can now be imported from the manufacturer's page. ALcad keeps the original file unchanged, records where it came from (address, file name, SHA-256 hash, time and license) and reports whether it is plain SPICE, PSpice, LTspice, encrypted or Verilog-A, so you know what will run before you build on it. In Cloud, imported models stay private to you.

For boards, manufacturing DRC checks a layout against a pinned, sourced manufacturer rule set. The checks were compared with KiCad 9 on a set of reference boards, and the results panel says which rules and which comparison it relies on.

In QEDA on the Linux desktop app, new parametric cells for a transmon pad, a quarter-wave CPW resonator and a feedline run DRC and then show an ideal CPW estimate of impedance and resonant frequency for the same geometry. Change an input and the old estimate is hidden until you run the check again.

Process design kits with their origins

When you choose a process design kit, the picker now shows where it comes from: the distribution link, its license terms, the routes to fabrication, how mature the upstream project is and what Digital Design Studio has verified. Kits that cannot be fabricated say so clearly. An expandable guide describes the open shuttle programs that can turn a design into real chips.

The simulation engines are also checked against problems with known exact answers: voltage dividers and RC, RL and RLC circuits for SPICE, Gaussian and erf profiles for diffusion, and plane waves, perfect conductors, Fresnel reflection and resonance for FDTD. Each check measures how quickly the error shrinks as the resolution increases.

Other changes

Updates that restart the app. On Windows, an in-app update now restarts Digital Design Studio instead of asking you to restart Windows.

Notifications at a glance. The dashboard shows a notification balloon, and the notification list is easier to scan.

Pick up where you left off. When you return to a window, your unsaved editor work and the panels you had open are still there.

A faster start in Cloud. The dashboard and the settings windows now load when you open them, so the first page of Cloud downloads much less code.

Fourteen languages. vFactory's views, tours and calculation panels are available in all 14 interface languages, like the rest of the app.

Known limitation. On computers with Intel Iris Xe graphics, shared GPU memory grows by about 16.6 MB each time you open and close the inside view of an EUV scanner, and by about 32–36 MB each time you switch 3D quality between Medium and Low. A later release fixes this.

Version 2.1.2 links design and manufacturing in one app: design a block in DDS, prepare its circuits and board in ALcad and follow it to wafers in vFactory. Open vFactory and start the tour to see where your designs are headed.


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